Towards Compiling SAC for the Xeon Phi Knights Corner and Knights Landing Architectures Strategies and Experiments

Xeon Phi is the common brand name of Intel's Many Integrated Core (MIC) architecture. The first commercially available generation Knights Corner and the second generation Knights Landing form a middle ground between modestly parallel desktop and standard server processor architectures and the massively parallel GPGPU architectures.
In this paper we explore various compilation strategies for the purely functional data-parallel array language SAC (Single Assignment C) to support both MIC architectures in the presence of entirely resource- and target-agnostic source code. Our particular interest lies in doing so with limited, or entirely without, user knowledge about the target architecture. We report on a series of experiments involving two classical benchmarks, Matrix Multiplication and Gaussian Blur, that demonstrate the level of performance that can be expected from compilation of abstract, purely functional source code to the Xeon Phi family of architectures.