Microthreading: model and compiler

There are two ways to improve processor performance, either by increasing the number of instructions issued per cycle or by increasing the speed of the processor’s clock. However, the former increases circuit complexity for diminishing returns and the latter increases power dissipation. Our Microthreading model proposes an alternative approach to ILP based on code fragmentation. These code fragments are called microthreads and they can be run concurrently on a CMP chip. This concurrency is explicitly described in the source file by using a new language μTC based on the C language. The compiler produces specific code which contains new ISA instructions. Those instructions permit a family of microthreads to be created which can be a collection of loop iterations or heterogeneous processes. This paper presents an overview of the Microthreading model and the compilation chain targeting this new architecture.