Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities

Modern application-specific integrated circuits (ASICs) are increasingly employed in domains where they must fulfill security requirements. Traditional ASIC design flows include numerous steps to ensure the correctness of a circuit and its freedom from manufacturing defects, but they do not cover security vulnerabilities. In this paper, we show how to leverage state-of-the-art electronic design automation (EDA) tools to validate the resistance of a circuit against fault injection attacks in early design steps (before fabrication). While the approach is generic, we demonstrate it on a specific physical attack vector: Fault Sensitivity Analysis (FSA). We show how existing tools (especially for logic and timing simulation) can be extended by custom scripts to assess the vulnerability of an implementation to such attacks.